"NSA Publishes Guidance on Characterizing Threats, Risks to DoD Microelectronics"

The National Security Agency's (NSA) Joint Federation Assurance Center (JFAC) Hardware Assurance Lab published a report titled "DoD Microelectronics: Levels of Assurance Definitions and Applications" to characterize the threats and risks faced by Custom Microelectronic Components (CMC) used in Department of Defense (DoD) systems. The Cybersecurity Technical Report describes a consistent and measurable approach to addressing assurance risks in the fabrication of CMC, which include Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA), and other custom or configurable microelectronic devices. This document defines three levels of hardware assurance and the steps required to apply them in the protection of DoD systems' custom microelectronic parts. The report was written by the NSA JFAC, which strengthens and supports DoD programs' microelectronics hardware assurance by providing vulnerability detection, analysis, and remediation capabilities. This article continues to discuss the new guidance published by NSA on characterizing threats and risks to DoD microelectronics. 

HSToday reports "NSA Publishes Guidance on Characterizing Threats, Risks to DoD Microelectronics"