"NSA Releases Series on Protecting DOD Microelectronics From Adversary Influence"

The National Security Agency's (NSA) Joint Federated Assurance Center (JFAC) Hardware Assurance Lab has made four Cybersecurity Technical Reports publicly available to help the Department of Defense (DOD) in protecting Field-Programmable gate array (FPGA)-based systems from adversary influence. The reports were created to help bolster the security of FPGAs, which are programmable microelectronic components, during their manufacturing, acquisition, programming, and initial attachment. The document "Field-Programmable Gate Array (FPGA) Overall Assurance Process" describes the process used by the NSA JFAC to develop threat categories and mitigations. This report allows teams to try performing the same quality assurance work on other types of microelectronic devices. The report "Field-Programmable Gate Array Best Practices — Threat Catalog" describes the high-level threat categories associated with FPGA devices at each Level of Assurance. This is part of the DOD Program Protection Plan's Trusted Systems and Networks stage. The "Field-Programmable Gate Array Level of Assurance 1 Best Practices" report includes mitigations for each relevant FPGA threat category at Level of Assurance 1, while the "Third-Party IP Review Process for Level of Assurance 1" report details a methodology for performing an engineering review of third-party intellectual property included in an FPGA design for Trojan detection. This article continues to discuss the series of reports released by NSA's JFAC Hardware Assurance Lab aimed at helping the DOD protect FPGA-based systems. 

NSA reports "NSA Releases Series on Protecting DOD Microelectronics From Adversary Influence"