Intellectual Property protection continues to be a matter of major research interest. The articles cited here look at hardware security and provenance and piracy prevention. They were published between May and August of 2014.

• Rostami, M.; Koushanfar, F.; Karri, R., "A Primer on Hardware Security: Models, Methods, and Metrics," Proceedings of the IEEE, vol.102, no.8, pp.1283, 1295, Aug. 2014. doi: 10.1109/JPROC.2014.2335155 Abstract: The multinational, distributed, and multistep nature of integrated circuit (IC) production supply chain has introduced hardware-based vulnerabilities. Existing literature in hardware security assumes ad hoc threat models, defenses, and metrics for evaluation, making it difficult to analyze and compare alternate solutions. This paper systematizes the current knowledge in this emerging field, including a classification of threat models, state-of-the-art defenses, and evaluation metrics for important hardware-based attacks.
  
  Keywords: pattern classification; security of data ;IC production supply chain; ad hoc threat models; evaluation metrics; hardware security; hardware-based attacks; hardware-based vulnerabilities; integrated circuit; threat models classification; Computer security; Hardware; Integrated circuit modeling; Security; Supply chain management; Trojan horses; Watermarking; Counterfeiting; IP piracy; hardware Trojans; reverse engineering; side-channel attacks (ID#:14-2948)
  
  URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860363&isnumber=6860340

• Rajendran, J.; Sinanoglu, O.; Karri, R., "Regaining Trust in VLSI Design: Design-for-Trust Techniques," Proceedings of the IEEE , vol.102, no.8, pp.1266,1282, Aug. 2014. doi: 10.1109/JPROC.2014.2332154 Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.
  
  Keywords: VLSI; cryptography; integrated circuit design; logic circuits; microprocessor chips; reverse engineering; DfTr techniques; IP cores; IP piracy; VLSI design; design-for-trust techniques; integrated circuit camouflaging; integrated circuit design flow; logic encryption; malicious circuits; regaining trust; reverse engineering; security vulnerabilities; split manufacturing; third-party intellectual property cores; trojan activation; unprotected design; very large scale integration design; Design methodology; Encryption; Hardware; integrated circuit modeling; Logic gates; Very large scale integration; Design automation; design for testability; security (ID#:14-2949)
  
  URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6856167&isnumber=6860340

• Rahman, M.T.; Forte, D.; Quihang Shi; Contreras, G.K.; Tehranipoor, M., "CSST: An Efficient Secure Split-Test for Preventing IC Piracy," North Atlantic Test Workshop (NATW), 2014 IEEE 23rd,pp.43,47, 14-16 May 2014. doi: 10.1109/NATW.2014.17 With the high costs associated with modern IC fabrication, most semiconductor companies have gone fabless, i.e., they outsource manufacturing of their designs to contract foundries. This horizontal business model has led to many well documented issues associated with untrusted foundries including IC overproduction and shipping improperly or insufficiently tested chips. Entering such chips in the supply chain can be catastrophic for critical applications. We propose a new Secure Split-Test to give control over testing back to the IP owner. Each chip is locked during test. The IP owner is the only entity who can interpret the locked test results and unlock passing chips. In this way, SST can prevent shipping overproduction and defective chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry and IP owner compared to the original version of the secure split test. The results demonstrate that our new technique is more secure than the original and with less communication barriers.
  
  Keywords: integrated circuit testing; supply chain management; CSST; IC fabrication ;IC overproduction; IC piracy prevention ;IC shipping; IP owner; communication barriers; efficient secure split-test; horizontal business model; outsource manufacturing; semiconductor companies; supply chain; Assembly; Foundries; IP networks; Integrated circuits; Security; Supply chains; Testing (ID#:14-2950)
  
  URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6875447&isnumber=6875429

Note:

Articles listed on these pages have been found on publicly available internet pages and are cited with links to those pages. Some of the information included herein has been reprinted with permission from the authors or data repositories. Direct any requests via Email to SoS.Project (at) SecureDataBank.net for removal of the links or modifications to specific citations. Please include the ID# of the specific citation in your correspondence.