Towards a Process to Forecast Vulnerability in Systems of Systems
ABSTRACT
The desire for tomorrow’s systems to rapidly collaborate and integrate information from distributed sources has increased the demand for Cyber Physical System (CPS) solutions. These solutions continue to grow in complexity, which currently correlates to larger threat from Cyber-attack. When designing these distributed collaborative CPS, a major challenge is managing the difference between the design and real implementation. These differences, or misalignments, create an aperture for access and an opportunity for Cyber vulnerabilities within underlying components to be exposed for exploitation.
This attack surface is a direct result of insufficient mechanism to identify, measure, and track cyber vulnerabilities, using only system design documents. The current state-of-design function in stovepipes with very little sharing between standalone systems design artifacts and the overall system of systems (SoS). Therefore, data files and formats have limitations in its ability to share that information. For instance, the integrated circuit design process is focused on meeting derived component requirements with little or no intent on scoping and defining requirements for undesired functionality. This is mainly due to the fact that component complexity has increased dramatically with each successive technology node, and that verification of the known good function is a major bottleneck. The inclusion of the undesired functionality would prove difficult and labor intensive because of all the undesirable states.
A solution we are presenting to this challenge is to employ a “Digital Thread” methodology to link digital design tools and representations for design, implementation, and life cycle management to create the ability to identify, measure, and track cyber vulnerabilities from systems engineering artifacts. We envision a new design-space framework that would provide system traceability (requirements, vulnerabilities, abnormalities, and ambiguities), and based on this knowledge provide forecasting of failure causalities for improved security (i.e. reduction of attack surface).
Our solution would create a new systems engineering toolchain to integrate a large corpus of digital design artifacts from system components (also called subsystems) to construct an end-to-end virtual representation of the SoS in an ultra-high fidelity modeling and simulation environment. A probabilistic framework to assess the unified model could then be used to quantify, forecast, and update system performance and capability. This process would provide designers the ability to forecast Cyber vulnerabilities at design time. The proposed solution simultaneously improves Cyber resiliency and drastically reduces costs by providing a new mechanism to assess Cyber vulnerabilities far left in the Systems Engineering ‘V’.
The ability to extend the ‘V’ model allows for the fine tuning of information through an iterative process which leads us on a path towards a Digital Twin. One of the products of the system engineering process is the baseline architecture. The baseline architecture begins the collection of information which is referred to as the Data/Model Repository (DMR). Once all of the design information is gathered, the analyst can setup the initial Design of Experiments (DOE). The analyst runs experiments and analyzes the results in an iterative methodology. The results of analysis lead to the identification of system artifacts. These artifacts are leveraged to generate forecast models of future components within a Digital Twin and integration into the baseline architecture. This information contains the baseline architecture, design and technical documents, physics based models of the system, 3D layout models, manufacturing and tooling capabilities, design tool limitations, and any other source of information about a system or sub-system. The collection of information is critical in the success of a designer’s ability to expose underlying faults which are possible for exploitation.
This new toolchain to aid in SoS systems engineering would provide system engineers a mechanism to iterate through environmental, thermal, electromagnetic and manufacturing variables in a Digital Twin of the system and assess apertures for Cyber attack. The ability to model the system leads to the forecasting of failure causalities. The reduction of faults in a system increases security and dependability, while reducing cost and uncertainty.
PRESENTER BIOGRAPHIES
Joseph Natarian (Member, IEEE) received the B.Sc. degree in electrical engineering and computer science from the Wright State University, Dayton, Ohio, in 2008. He is currently pursuing the M.Sc in electrical engineering from the University of Dayton, Dayton, Ohio. Since 2007 he has be supporting the Air Force Research Laboratory (AFRL) in Dayton, Ohio. From 2007 to 2008, he worked for General Dynamics, Advanced Information Systems, where he supported multiple research projects in the Collaborative Interfaces Branch of the Warfighter Interface Division within AFRL. In 2008 he joined the Civil Service as a member of the in-house research team in the Distributed Collaborative Sensor System Technology Branch of the Autonomic Trusted Sensing for Persistent Intelligence Technology Office within AFRL. In 2011 Mr. Natarian took a position in the Advanced Programs Division (AFRL/RYZ), where he is currently a systems engineer. As a researcher, Mr. Natarian collaborates on numerous Defense Advanced Research Project Agency (DARPA) research programs such which explore challenges with architecting and/or integrating complex systems such as trust, tools to evaluate security, and techniques for identifying and traversing threat vectors via control flow and data flow analysis.
Mr. Marvin Worst is the National Air and Space Intelligence Center (NASIC) Command Section’s senior integrator for Cyber Intelligence Issues. Serving in this role since 2011, he provides executive-level and line guidance for various special topics and customers involved in the DOD, USAF, and Intelligence Community’s cyber enterprise. He also supports research and development effort to establish new capabilities. Mr Worst’s began his career at NASIC in 2000 and served in several analytic positions in the RADAR/MASINT and C4-IO disciplines. Prior to joining the US Government, Mr. Worst worked for multiple companies including Motoman Inc., General Electric-Aerospace Division, and Ball Aerospace. There he gained practical engineering experience while designing and developing manufacturing robotics, jet engines, and radar and space software. Mr Worst holds a variety of academic degrees. He completed an AS in Automated Software/Robotics from University of Cincinnati in 1992. He further advanced his educational pursuits by achieving a BS and MS in Computer Engineering from Wright State University in 1996 and 1999, respectively.
Dr. Bruce Howard is the Director of Research and Development at Wright State Research Institute. His current research includes embedded systems security for laboratory analytical equipment, particularly biocyberphysical systems, vulnerability forecasting from incomplete ASIC design information, and computational epigenomics. Prior to joining WSRI, Mr. Howard was the Director of the Center for Nanoscale Engineering at System Planning Corporation, where he developed, demonstrated, and transitioned high risk tailored solutions for a variety of customers. Mr. Howard holds a MS in Systems Engineering, and is currently pursuing a PhD in Computer Science and Engineering with a focus in bioinformatics.