Keynote: Implications of Systems Architectures of Tomorrow



As various economical and technological factors collide, the next generation of computing systems – from the edge to the cloud – will start to look very different from how today’s systems are being designed and optimized.  The oscillation between aggregation and disaggregation of resources, pivots to advanced 3D heterogeneous integration in packages, chiplet architectures and interoperable non-Ethernet fabrics, and economic challenges with scalable systems will result in a “shared everything” platform architecture.  This approach will raise new challenges in software models, but more importantly will introduce new avenues and surfaces for accidental and malicious corruptions or information leakage.

While some aspects of this are being carefully considered as ingredients are designed, history tells us that the industry will have a failure of imagination – and that unprecedented opportunities for new classes of information leakage will emerge.  In this talk, I will explore where we are at, the challenges that are driving changes, what future systems will look like, and the challenges that these may raise on users and security models.  I will end by suggesting a path for the future to address some of these challenges.


Dr. Joshua Fryman (PhD), Intel Fellow, received his Ph.D. from Georgia Institute of Technology, and B.S. degree from University of Florida. He is a Senior Member of IEEE. From 2005-2012, he was with the Intel Labs aside from a brief tour from 2009-2010 in the Software Solutions Group working on virtual ISA and support for what became Xeon Phi. Since 2012, he has led a vertically integrated applied R&D team as part of Intel’s Office of the CTO with Datacenter Technologies (2012-2020) and Intel’s Office of the CTO (2020-present). His research interests includes novel microprocessor architecture, co-design of workloads and systems, disaggregated system architecture, high-performance computing, embedded systems, novel memory architectures, photonic chip networks, and at-scale system fabrics. He has been lead architect or PI for multiple advanced research programs from DARPA, IARPA, DOE, and commercial entities since 2010.  He has over 16 public peer-reviewed publications, holds over 20 granted patents, solely authored one book on the Intel Larrabee architecture shipped with every unit, and supports multiple STEAM activities and diversity programs.

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  • HCSS Conference 2023
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  • HCSS 2023
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