Post-quantum cryptography (PQC) depends on large, short-lived secrets whose lifetime at the hardware boundary must be tightly controlled: even brief residency in conventional volatile memory exposes them to microarchitectural leakage, DMA visibility, speculative execution, and delayed software zeroization. This paper introduces a CMOS-realizable measurement–collapse primitive that enforces read-once semantics at the digital interface: the first authorized read discloses a stored value and, within the same propagation event in the synthesized design, triggers a deterministic collapse that prevents the value from being re-issued through the modeled interface. This logical measurement–collapse behavior captures the core semantic requirement for PQC-era ephemeral keying, while recognizing that the underlying storage elements in the present FPGA realization are still conventional CMOS registers; eliminating residual electrical persistence in a fabricated ASIC is explicitly deferred to future work. A 1024-cell FPGA prototype on an Intel Cyclone V validates this behavior for 8+8-bit cells, with per-cell costs of ∼17.1 ALMs and 26.7 registers and single-cycle collapse timing at 50 MHz. Within this prototype, we empirically demonstrate (i) exactly one disclosure per cell, (ii) immediate RTL-level invalidation of the stored value, and (iii) no re-issuance of that value under repeated or unauthorized accesses at the digital boundary. The post-collapse stream is treated solely as an obfuscation mechanism in this work; no entropy, randomness, or NIST SP 800-90B/C certification claims are made for it. We formalize an idealized measurement–collapse model, outline how the primitive can serve as a hardware-enforced store for PQC-derived ephemeral secrets (e.g., ML-KEM shared secrets in TLS 1.3), and discuss design considerations for a future ASIC realization. Constant-time hardening, certified entropy evaluation, physical-security characterization against invasive attacks, and demonstration of true electrical non-persistence at the device level are explicitly identified as future work.