Internet of Things (IoT) has become extremely prominent for industrial applications and stealthy modification deliberately done by insertion of Hardware Trojans has increased widely due to globalization of Integrated Circuit (IC) production. In the proposed work, Hardware Trojan is detected at the gate level by considering netlist of the desired circuits. To mitigate with golden model dependencies, proposed work is based on unsupervised detection of Hardware Trojans which automatically extracts useful features without providing clear desired outcomes. The relevant features from feature dataset are selected using eXtreme Gradient Boosting (XGBoost) algorithm. Average True Positive Rate (TPR) is improved about 30\% by using Clustering-based local outlier factor (CBLOF) algorithm when compared to local outlier factor algorithm. The simulation is employed on Trust-HUB circuits and achieves an average of 99.83\% True Negative Rate (TNR) and 99.72\% accuracy which shows the efficiency of the detection method even without labelling data.

Hardware Trojans (HT) are minuscule circuits embedded by an adversary for malicious purposes. Such circuits posses stealthy nature and can cause disruption upon activation. To detect the presence of such circuits, appropriate test vectors need to be applied. In this regard, the genetic algorithm (GA) seems to be the most promising technique due to its exploration capability. However, like most of the existing techniques, GA also suffers from exploring the huge search space. In this article a GA based methodology is proposed incorporating the information about potential inputs into it. Experimental results analysis signifies that the identification of the relevant inputs for GA provides an optimal solution. The significance of proposed methodology is endorsed by applying the proposed GA technique on different ISCAS ’85 benchmark circuits. A noteworthy improvement on run time is observed while simultaneously providing improved test set quality than the state-of-the art technique.

Recently, hardware Trojan has become a serious security concern in the integrated circuit (IC) industry. Due to the globalization of semiconductor design and fabrication processes, ICs are highly vulnerable to hardware Trojan insertion by malicious third-party vendors. Therefore, the development of effective hardware Trojan detection techniques is necessary. Testability measures have been proven to be efficient features for Trojan nets classification. However, most of the existing machine-learning-based techniques use supervised learning methods, which involve time-consuming training processes, need to deal with the class imbalance problem, and are not pragmatic in real-world situations. Furthermore, no works have explored the use of anomaly detection for hardware Trojan detection tasks. This paper proposes a semi-supervised hardware Trojan detection method at the gate level using anomaly detection. We ameliorate the existing computation of the Sandia Controllability/Observability Analysis Program (SCOAP) values by considering all types of D flip-flops and adopt semi-supervised anomaly detection techniques to detect Trojan nets. Finally, a novel topology-based location analysis is utilized to improve the detection performance. Testing on 17 Trust-Hub Trojan benchmarks, the proposed method achieves an overall 99.47\% true positive rate (TPR), 99.99\% true negative rate (TNR), and 99.99\% accuracy.

There have been reports of threats that cause electromagnetic information leakage by inserting Hardware Trojans (HT) into the signal traces around components on the printed circuit board (PCB). In this threat, the HT insertion is assumed not only at the manufacturing stage but also during the in-transit or in the field after shipment, and the threat may extend to devices that are not considered to be threatened by HT insertion implemented inside conventional ICs. This paper discusses the detection method for the HT insertion, which is implementable on a PCB without external measurement equipment. Additionally, we validate the method in more practical situations, detecting the HT on populated PCBs. The method employs an on-chip touch sensor to measure the changes in electrical characteristics caused by HT insertion. Specifically, HT insertion is detected by observing the change in capacitance and insulation resistance associated with HT insertion using the on-chip sensor, and detecting the difference from the measurement result when HT is not inserted to signal traces. In the experiment, we build an evaluation environment, which emulates a populated PCB, based on the HT insertion method reported in previous studies and observe the change in capacitance and insulation resistance on the connected signal trace using a microprocessor equipped with a constant current source and an analog-digital converter that constitute the onchip sensor. Then, we show that HT insertion on the signal trace can be detected from the output values of the on-chip sensor before and after HT insertion.

Emerging Analog Trojans such as A2, large-delay Trojans, and row-hammer have been shown to be more stealthier than previously known digital Trojans. They are smaller sized, do not rely on inputs for triggering, and the trigger for their payload can be made arbitrarily delayed, like a ticking time bomb. Furthermore, analog Trojans can easily evade detection due to their novel nature and incompatibility with the digital design and validation flow. In this paper, we propose a current signature-based detection scheme, which can effectively catch various analog Trojans at both run-time and production time validation. The paper includes techniques that advance Trojan detection method through incorporating detection of transient variation in the power supply current. Proposed current-sensor can sense currents down to 10s of nano-Amps improving over prior power sensing based techniques. Further, a configurable design of current sensor is developed to enable large range sensing capability. The design is also developed to be compatible with the digital design flow and can be logic obfuscated. This detection method can be used at run-time to potentially fence off activation of analog Trojans in the field through early warning signals. The commercial 65nm CMOS technology is utilized to verify the proposed idea.

This work proposes a novel hardware Trojan detection method that leverages static structural features and behavioral characteristics in field programmable gate array (FPGA) netlists. Mapping of hardware design sources to look-up-table (LUT) networks makes these features explicit, allowing automated feature extraction and further effective Trojan detection through machine learning. Four-dimensional features are extracted for each signal and a random forest classifier is trained for Trojan net classification. Experiments using Trust-Hub benchmarks show promising Trojan detection results with accuracy, precision, and F1-measure of 99.986\%, 100\%, and 99.769\% respectively on average.

In recent years, with the globalization of semiconductor processing and manufacturing, integrated circuits have gradually become vulnerable to malicious attackers. In order to detect Hardware Trojans (HTs) hidden in integrated circuits, it has become one of the hottest issues in the field of hardware security. In this paper, we propose to apply Principal Component Analysis (PCA) and Support Vector Machine (SVM) to hardware Trojan detection, using PCA algorithm to extract features from small differences in side channel information, and then obtain the principal components. The SVM detection model is optimized by means of cross-validation and logarithmic interval. Finally, it is determined whether the original circuit contains a hardware Trojan. In the experiment, we use the SAKURA-G FPGA board, Agilent oscilloscope, and ISE simulation software to complete the experimental work. The test results of five different HTs show that the average True Positive Rate (TPR) of the proposed method for HTs can reach 99.48\%, along with an average True Negative Rate (TNR) of 99.2\%, and an average detection time of 9.66s.

In order to visually present all kinds of hardware Trojan horse detection methods and their relationship, a method is proposed to construct the knowledge graph of hardware Trojan horse detection technology. Firstly, the security-related knowledge of hardware Trojan horse is analyzed, then the entity recognition and relationship extraction are carried out by using BiLSTM-CRF model, and the construction of knowledge graph is completed. Finally, the knowledge is stored and displayed visually by using graph database neo4j. The combination of knowledge graph and hardware Trojan security field can summarize the existing detection technologies, provide a basis for the analysis of hardware Trojans, vigorously promote the energy Internet security construction, and steadily enhance the energy Internet active defense capability.

Outsourcing Integrated Circuits(ICs) pave the way for including malicious circuits commonly known as Hardware Trojans. Trojans can be divided into functional and parametric Trojans. Trojans of the first kind are made by adding or removing gates to or from the golden reference design. Trojans of the following type, the golden circuit is modified by decreasing connecting wire’s thickness, exposing the chip to radiation, etc. Hardware Trojan detection schemes can be broadly classified into dynamic and static detection schemes depending on whether or not the input stimulus is applied. The proposed method aims to detect functional Trojans using the static detection method. The work proposes a generic, scalable Trojan detection method. The defender does not have the luxury of knowing the type of Trojan the circuit is infected with, making it difficult for accurate detection. In addition, the proposed method does not require propagating the Trojan effect on the output, magnifying the Trojan effect, or any other voting or additional algorithms to accurately detect the Trojan as in previous literature. The proposed method analyses synthesis reports for Trojan detection. Game theory, in addition, aids the defender in optimal decisionmaking. The proposed method has been evaluated on ISCAS’85 and ISCAS’89 circuits. The proffered method detects various types of Trojans of varying complexities in less time and with 100\% accuracy.