Multicore Computing Security - Flush-based cache attacks like Flush+Reload and Flush+Flush are highly precise and effective. Most of the flushbased attacks provide high accuracy in controlled and isolated environments where attacker and victim share OS pages. However, we observe that these attacks are prone to low accuracy on a noisy multi-core system with co-running applications. Two root causes for the varying accuracy of flush-based attacks are: (i) the dynamic nature of core frequencies that fluctuate depending on the system load, and (ii) the relative placement of victim and attacker threads in the processor, like same or different physical cores. These dynamic factors critically affect the execution latency of key instructions like clflush and mov, rendering the pre-attack calibration step ineffective.

Multicore Computing Security - Dynamic Voltage and Frequency Scaling (DVFS) is a widely deployed low-power technology in modern systems. In this paper, we discover a vulnerability in the implementation of the DVFS technology that allows us to measure the processor’s frequency in the userspace. By exploiting this vulnerability, we successfully implement a covert channel on the commercial Intel platform and demonstrate that the covert channel can reach a throughput of 28.41bps with an error rate of 0.53\%. This work indicates that the processor’s hardware information that is unintentionally leaked to the userspace by the privileged kernel modules may cause security risks.

Multicore Computing Security - Machines with multiple cores have become more and more popular. In order to fully utilize their parallel computation ability, efficient scheduling algorithm plays an important role. A good scheduler should output the reasonably good result quickly but most of the current schedulers fail to achieve this goal and always have to compromise between the running time and result quality. In response to the above concerns, this paper proposes one algorithm, Longest Path First In (LPFI), to do scheduling efficiently and effectively for multi-core. This algorithm uses a deterministic allocation mechanism to prioritize processes which are in long dependency chain. The experiment results show that, compared with greedy scheduling algorithm, LPFI has around 10\% improvement in the final result and can output the optimal result much faster than integer linear programming (ILP) scheduler.

Multicore Computing Security - Automobiles have become an indispensable part of life for both business and pleasure in today s society. Because of the long-term continuous work, fatigue presents a great danger to ride-sharing and truck drivers. Therefore, this paper aims to design a device that provides valuable feedback by evaluating driver status and surroundings. A gradient judgment is made through lane detection and face detection. When a dangerous condition is detected, the driver will be alerted by music and audio announcements with different degrees. The system also has two additional functions. First, a digital record-keeping to assist the professional driver. The other is a security system that if a stranger starts the car, a text message will be sent to the owner s phone. Compared with those in previous works, the proposed system s efficacy and efficiency are validated qualitatively and quantitatively in driver fatigue detection.

Multicore Computing Security - The automotive industry has recently emphasized reducing the number of Electronic Control Units (ECUs) installed in vehicles for economic and ecological reasons. This reduction means that the design and verification must be independent of the vehicle’s final choice of (MC)SoCs, knowing they will evolve as time passes. To that end, dataflow Models of Computation and Communication (MoCCs) are powerful tools for maintaining this independence. A subclass of dataflow MoCCs –deterministic dataflow MoCCs– is of particular interest since it allows designers to derive safety and security properties at compile-time. This work proposes a short survey of the existing deterministic dataflow MoCCs. We describe the properties of each dataflow MoCC and present an expressiveness hierarchy of dataflow MoCCs adjustable to designers’ needs.

Multicore Computing Security - With the continuous improvement of processor performance requirements, technologies such as superscalar, deep pipeline, and multi-core which can improve instruction parallelism are frequently used. Under this technical background, branch prediction errors will increase the delay used to flush the pipeline and greatly reduce the performance of the processor. Therefore, for high-performance processors, branch predictors with high prediction accuracy are particularly important. Based on the open source RISC-V processor core SweRV EH1, this paper adopts two prediction predictors, the hybrid predictor, and the TAGE predictor to improve the prediction performance of the original processor. This paper uses the riscv-tests selfchecking test scheme to verify the instruction set of the optimized processor and completes the prototype verification on the Kintex7 KC705 FPGA. Based on PowerStone and CoreMark test programs, this paper separately evaluates the branch prediction performance and processor performance of the processor core with two kinds of branch predictors. Experiments show that the implementation of the hybrid predictor and the TAGE predictor respectively improves the branch prediction accuracy of PowerStone programs by 3.65\% and 3.39\%; the average branch prediction rate respectively reaches 85.98\% and 90.06\%. The performance of SweRV EH1 is respectively improved by 2.56\% and 5.43\%.

Multicore Computing Security - This paper deals with hash based secure chaotic steganography technique for hiding secret information, into the cover image. Hash function has been used in the proposed work for computing the Non LSB positions for hiding the secret data bits. Secret is encoded with chaotic sequences and randomness of the sequences has been validated with NIST test suite. Shared memory implementation for faster execution of the proposed security technique has been done in OpenMP platform. Sequential and the parallel versions of the techniques have been implemented in C++, OpenMP and simulated in the Intel Haswell processor based multi-core environment. With the advantages offered by multicore processors the proposed technique ensures low time complexity. Significant speedup and linear scalability have been reported with increase in the number of threads. Standard statistical validation test results viz. PSNR, Euclidean distance, histogram analysis, SSIM index applied to validate the quality of stego image show satisfactory results.

Multicore Computing Security - In this paper, we study the effectiveness of denial-ofservice (DoS) attacks on Intel’s heterogeneous multicore systemon-chips with integrated GPU (iGPU) in which the last level cache (LLC) and the main memory subsystem are shared between the multicore CPU and the iGPU. Using two Intel processors with iGPU, we evaluate four different DoS attacks, three CPU based and one iGPU based, and show they can induce very high degree of shared resource contention and thus dramatically slowdown the victim’s execution time. We further evaluate the effectiveness of Intel’s recent hardware based shared resource isolation mechanisms, namely Intel Cache Allocation Technology (CAT) and Graphics Technology Class of Service (GT COS), which provide shared LLC partitioning capability for the CPU cores and the iGPU, respectively, in defending against these DoS attacks. Using both synthetic and real-world benchmarks, we find that hardware based LLC partitioning mechanisms does provide spatial LLC space isolation but does not necessarily provide temporal isolation.

Multicore Computing Security - Physical memories or RAMs are essential components in a computer system to hold temporary information required for both software and hardware to work properly. When a system’s security is compromised (e.g., due to a malicious application), sensitive information being held in the memories can be leaked out for example to “the cloud”. The RISC-V privileged architecture standard adopts a method called Physical Memory Protection (PMP) to segregate a system’s memory into regions with different policy and permissions to prevent unprivileged software from accessing unauthorized regions. However, PMP does not prevent malicious software from hijacking an Input/Output (IO) device with Direct Memory Access (DMA) capability to indirectly gain unauthorized accesses and hence, a similar method commonly termed as “IOPMP” is being worked on in the RISC-V community. This paper describes an early implementation of IOPMP and how it is used to protect physical memory regions in a RISC-V system. Then, the potential performance impact of IOPMP is briefly elaborated. There are still work to be done and this early IOPMP implementation allows various aspects of the protection method such as its scalability, practicality, and effectiveness etc. to be studied for future enhancement.